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1 for more information www.linear.com/ltc2348-18 typical a pplica t ion fea t ures descrip t ion octal, 18-bit, 200ksps differential 10.24v input softspan adc with wide input common mode range the lt c ? 2348-18 is an 18-bit, low noise 8-channel si - multaneous sampling successive approximation register ( sar) adc with differential, wide common mode range inputs. operating from a 5v low voltage supply, flexible high voltage supplies , and using the internal reference and buffer, each channel of this softspan tm adc can be independently configured on a conversion-by-conversion basis to accept 10.24v, 0v to 10.24v, 5.12v, or 0v to 5.12v signals. individual channels may also be disabled to increase throughput on the remaining channels. the wide input common mode range and 118db cmrr of the ltc2348-18 analog inputs allow the adc to directly digitize a variety of signals, simplifying signal chain de - sign. this input signal flexibility, combined with 3lsb inl , no missing codes at 18 bits, and 96.7db snr, makes the ltc2348-18 an ideal choice for many high voltage applications requiring wide dynamic range. the ltc2348-18 supports pin-selectable spi cmos (1.8v to 5v) and lvds serial interfaces . between one and eight lanes of data output may be employed in cmos mode, allowing the user to optimize bus width and throughput. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7705765, 7961132, 8319673. other patents pending. a pplica t ions n 200ksps per channel throughput n eight simultaneous sampling channels n 3lsb inl (maximum, 10.24v range) n guaranteed 18-bit, no missing codes n differential, wide common mode range inputs n per-channel softspan input ranges: 10.24v, 0v to 10.24v, 5.12v, 0v to 5.12v n 96.7db single-conversion snr (typical) n ?109db thd (typical) at f in = 2khz n 118db cmrr (typical) at f in = 200hz n rail-to-rail input overdrive tolerance n guaranteed operation to 125c n integrated reference and buffer (4.096v) n 2.5v to 5v external reference input range n spi cmos (1.8v to 5v) and lvds serial i/o n internal conversion clock, no cycle latency n 140mw power dissipation (typical) n 48-lead (7mm x 7mm) lqfp package n programmable logic controllers n industrial process control n power line monitoring n test and measurement integral nonlinearity vs output code and channel 0.1f 2.2f 0.1f 0.1f 1.8v to 5v 5v 15v ?15v sample clock 234818 ta01a s/h s/h s/h s/h s/h s/h s/h s/h mux v cc v dd v ddlbyp ov dd eight simultaneous sampling channels differential inputs in + /in ? with wide input common mode range +10v 0v ?10v fully differential +10v 0v ?10v true bipolar +10v 0v ?10v arbitrary +10v 0v ?10v unipolar sdo0 sdo7 scko scki sdi cs busy cnv ? ? ? ? ? ? lvds/ cmos pd in0 + in0 ? in7 + in7 ? 18-bit sar adc cmos or lvds i/o interface 0.1f refin 47f 0.1f gnd refbuf v ee ltc2348-18 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 inl error (lsb) vs output code integral nonlinearity 234818 g01 ltc 2348-18 234818f 10.24v range true bipolar drive (in ? = 0v) all channels output code ?131072 ?65536 0 65536 131072 ?2.0
2 for more information www.linear.com/ltc2348-18 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v cc ) ..................... C0. 3 v to (v ee + 40v) supply voltage (v ee ) ................................ C1 7. 4 v to 0.3 v supply voltage difference (v cc C v ee ) ...................... 40 v su pply voltage (v dd ) .................................................. 6v su pply voltage ( ov dd ) ................................................ 6v in ternal regulated supply bypass (v ddlbyp ) ... ( note 3) a nalog input voltage in 0 + to in 7 + , in 0 C to in 7 C ( note 4) ......... ( v ee C 0.3 v ) to ( v cc + 0.3 v) refin .................................................... C 0.3 v to 2.8 v re fbuf , cnv ( note 5) ............. C 0.3 v to (v dd + 0.3 v) digital input voltage ( note 5) ..... C 0.3 v to ( ov dd + 0.3 v) digital output voltage ( note 5) .. C 0.3 v to ( ov dd + 0.3 v) power dissipation .............................................. 50 0 mw operating temperature range ltc 23 48 c ................................................ 0 c to 70 c ltc 23 48 i ............................................. C 40 c to 85 c ltc 23 48 h .......................................... C4 0 c to 125 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 in6 ? in6 + in5 ? in5 + in4 ? in4 + in3 ? in3 + in2 ? in2 + in1 ? in1 + 13 14 15 16 17 18 19 20 21 22 23 24 in0 ? in0 + gnd v cc v ee gnd refin gnd refbuf pd lvds/ cmos cnv 48 47 46 45 44 43 42 41 40 39 38 37 in7 + in7 ? gnd v ee gnd v dd v dd gnd v ddlbyp cs busy sdi sdo7 sdo ? /sdo6 sdo + /sdo5 scko ? /sdo4 scko + /scko ov dd gnd scki ? /scki scki + /sdo3 sdi ? /sdo2 sdi + /sdo1 sdo0 top view lx package 48-lead (7mm 7mm) plastic lqfp t jmax = 150c, ja = 53c/w o r d er i n f or m a t ion lead free finish tray part marking* package description temperature range ltc2348clx-18#pbf ltc2348clx-18#pbf ltc2348lx-18 48-lead (7mm 7mm) plastic lqfp 0c to 70c ltc2348ilx-18#pbf ltc2348ilx-18#pbf ltc2348lx-18 48-lead (7mm 7mm) plastic lqfp C40c to 85c ltc2348hlx-18#pbf ltc2348hlx-18#pbf ltc2348lx-18 48-lead (7mm 7mm) plastic lqfp C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. * the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ ltc 2348-18 234818f
3 for more information www.linear.com/ltc2348-18 e lec t rical c harac t eris t ics c onver t er c harac t eris t ics symbol parameter conditions min typ max units v in + absolute input range (in0 + to in7 + ) (note 7) l v ee v cc C 4 v v in C absolute input range (in0 C to in7 C ) (note 7) l v ee v cc C 4 v v in + C v in C input differential voltage range softspan 7: 2.5 ? v refbuf range ( note 7) softspan 6: 2.5 ? v refbuf /1.024 range ( note 7) softspan 5: 0 v to 2.5 ? v refbuf range ( note 7) softspan 4: 0 v to 2.5 ? v refbuf /1.024 range ( note 7) softspan 3: 1.25 ? v refbuf range ( note 7) softspan 2: 1.25 ? v refbuf /1.024 range ( note 7) softspan 1: 0 v to 1.25 ? v refbuf range ( note 7) l l l l l l l C2.5 ? v refbuf C2.5 ? v refbuf /1.024 0 0 C1.25 ? v refbuf C1.25 ? v refbuf /1.024 0 2.5 ? v refbuf 2.5 ? v refbuf /1.024 2.5 ? v refbuf 2.5 ? v refbuf /1.024 1.25 ? v refbuf 1.25 ? v refbuf /1.024 1.25 ? v refbuf v v v v v v v v cm input common mode voltage range (note 7) l v ee v cc C 4 v v in + C v in C input differential overdrive tolerance (note 8) l ?(v cc ? v ee ) (v cc ? v ee ) v i in analog input leakage current l C1 1 a c in analog input capacitance sample mode hold mode 50 10 pf pf cmrr input common mode rejection ratio v in + = v in ? = 18v p-p 200hz sine l 100 118 db v ihcnv cnv high level input voltage l 1.3 v v ilcnv cnv low level input voltage l 0.5 v i incnv cnv input current v in = 0v to v dd l C10 10 a symbol parameter conditions min typ max units resolution l 18 bits no missing codes l 18 bits transition noise softspans 7 and 6: 10.24v and 10v ranges softspans 5 and 4: 0v to 10.24v and 0v to 10v ranges softspans 3 and 2: 5.12v and 5v ranges softspan 1: 0v to 5.12v range 1.3 2.6 2.0 4.0 lsb rms lsb rms lsb rms lsb rms inl integral linearity error softspans 7 and 6: 10.24 v and 10 v ranges ( note 10) softspans 5 and 4: 0 v to 10.24 v and 0 v to 10 v ranges ( note 10) softspans 3 and 2: 5.12 v and 5 v ranges ( note 10) softspan 1: 0 v to 5.12 v range ( note 10) l l l l C3 C4 C2.5 C2.5 1 1.5 0.75 0.75 3 4 2.5 2.5 lsb lsb lsb lsb dnl differential linearity error (note 11) l ?0.9 0.2 0.9 lsb zse zero-scale error (note 12) l ?550 80 550 v zero-scale error drift 2 v/c fse full-scale error (note 12) l ?0.1 0.025 0.1 %fs full-scale error drift 2.5 ppm/c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 6) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) ltc 2348-18 234818f
4 for more information www.linear.com/ltc2348-18 dyna m ic a ccuracy i n t ernal r e f erence c harac t eris t ics symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio softspans 7 and 6: 10.24v and 10v ranges, f in = 2khz softspans 5 and 4: 0 v to 10.24 v and 0 v to 10 v ranges, f in = 2khz softspans 3 and 2: 5.12v and 5v ranges, f in = 2khz softspan 1: 0v to 5.12v range, f in = 2khz l l l l 93.0 87.6 90.0 84.2 96.5 90.6 93.2 87.3 db db db db snr signal -to-noise ratio softspans 7 and 6: 10.24v and 10v ranges, f in = 2khz softspans 5 and 4: 0 v to 10.24 v and 0 v to 10 v ranges, f in = 2khz softspans 3 and 2: 5.12v and 5v ranges, f in = 2khz softspan 1: 0v to 5.12v range, f in = 2khz l l l l 93.7 87.7 90.2 84.3 96.7 90.7 93.2 87.3 db db db db thd t otal harmonic distortion softspans 7 and 6: 10.24v and 10v ranges, f in = 2khz softspans 5 and 4: 0 v to 10.24 v and 0 v to 10 v ranges, f in = 2khz softspans 3 and 2: 5.12v and 5v ranges, f in = 2khz softspan 1: 0v to 5.12v range, f in = 2khz l l l l C109 C111 C113 C114 C101 C104 C104 C103 db db db db sfdr spurious free dynamic range softspans 7 and 6: 10.24v and 10v ranges, f in = 2khz softspans 5 and 4: 0 v to 10.24 v and 0 v to 10 v ranges, f in = 2khz softspans 3 and 2: 5.12v and 5v ranges, f in = 2khz softspan 1: 0v to 5.12v range, f in = 2khz l l l l 101 105 105 105 110 112 114 115 db db db db channel -to-channel crosstalk one channel converting 18v p-p 200hz sine in 10.24v range, crosstalk to all other channels ?109 db C3db input bandwidth 7 mhz aperture delay 1 ns aperture delay matching 150 ps aperture jitter 3 ps rms transient response full-scale step, 0.005% settling 360 ns symbol parameter conditions min typ max units v refin internal reference output voltage 2.043 2.048 2.053 v internal reference temperature coefficient (note 14) l 5 20 ppm/c internal reference line regulation v dd = 4.75v to 5.25v 0.1 mv/v internal reference output impedance 20 k v refin refin voltage range refin overdriven (note 7) 1.25 2.2 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (notes 9, 13) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) ltc 2348-18 234818f
5 for more information www.linear.com/ltc2348-18 r e f erence b u ff er c harac t eris t ics symbol parameter conditions min typ max units v refbuf reference buffer output voltage refin overdriven, v refin = 2.048v l 4.091 4.096 4.101 v refbuf voltage range refbuf overdriven (notes 7, 15) l 2.5 5 v refbuf input impedance v refin = 0v, buffer disabled 13 k i refbuf refbuf load current v refbuf = 5v, 8 channels enabled (notes 15, 16) v refbuf = 5v, acquisition or nap mode (note 15) l 1.5 0.39 1.9 ma ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) digi t al i npu t s an d digi t al o u t pu t s symbol parameter conditions min typ max units cmos digital inputs and outputs v ih high level input voltage l 0.8???ov dd v v il low level input voltage l 0.2???ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i out = C500a l ov dd ?C?0.2 v v ol low level output voltage i out = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C50 ma i sink output sink current v out = ov dd 50 ma lvds digital inputs and outputs v id differential input voltage l 200 350 600 mv r id on-chip input termination resistance cs = 0v, v icm = 1.2v cs = ov dd l 90 106 10 125 m v icm common-mode input voltage l 0.3 1.2 2.2 v i icm common-mode input current v in + = v in C = 0v to ov dd l C10 10 a v od differential output voltage r l = 100 differential termination l 275 350 425 mv v ocm common-mode output voltage r l = 100 differential termination l 1.1 1.2 1.3 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) ltc 2348-18 234818f
6 for more information www.linear.com/ltc2348-18 p ower r equire m en t s symbol parameter conditions min typ max units v cc supply voltage l 0 38 v v ee supply voltage l C16.5 0 v v cc ? v ee supply voltage difference l 10 38 v v dd supply voltage l 4.75 5.00 5.25 v i vcc supply current 200ksps sample rate, 8 channels enabled acquisition mode nap mode power down mode l l l l 1.8 3.8 0.7 1 2.2 4.5 0.9 15 ma ma ma a i vee supply current 200ksps sample rate, 8 channels enabled acquisition mode nap mode power down mode l l l l C2.8 C4.9 C1.1 C15 C2.2 C4.0 C0.8 C1 ma ma ma a cmos i/o mode ov dd supply voltage l 1.71 5.25 v i vdd supply current 200ksps sample rate, 8 channels enabled 200ksps sample rate , 8 channels enabled, v refbuf = 5v ( note 15) acquisition mode nap mode power down mode (c-grade and i-grade) power down mode (h-grade) l l l l l l 15.2 13.4 1.6 1.4 65 65 17.5 15.4 2.1 1.9 175 450 ma ma ma ma a a i ovdd supply current 200ksps sample rate, 8 channels enabled (c l = 25pf) acquisition or nap mode power down mode l l l 1.6 1 1 2.6 20 20 ma a a p d power dissipation 200ksps sample rate, 8 channels enabled acquisition mode nap mode power down mode (c-grade and i-grade) power down mode (h-grade) l l l l l 140 125 30 0.36 0.36 169 152 40 1.4 2.8 mw mw mw mw mw l vds i/o mode ov dd supply voltage l 2.375 5.25 v i vdd supply current 200ksps sample rate, 8 channels enabled 200ksps sample rate , 8 channels enabled, v refbuf = 5v ( note 15) acquisition mode nap mode power down mode (c-grade and i-grade) power down mode (h-grade) l l l l l l 17.7 16.1 3.2 3.0 65 65 20.4 18.5 3.8 3.7 175 450 ma ma ma ma a a i ovdd supply current 200ksps sample rate, 8 channels enabled (r l = 100) acquisition or nap mode (r l = 100) power down mode l l l 7 7 1 8.5 8.0 20 ma ma a p d power dissipation 200ksps sample rate, 8 channels enabled acquisition mode nap mode power down mode (c-grade and i-grade) power down mode (h-grade) l l l l l 166 151 55 0.36 0.36 199 180 69 1.4 2.8 mw mw mw mw mw the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) ltc 2348-18 234818f
7 for more information www.linear.com/ltc2348-18 a d c ti m ing c harac t eris t ics symbol parameter conditions min typ max units f smpl maximum sampling frequency 8 channels enabled l 200 ksps t cyc time between conversions 8 channels enabled l 5 s t conv conversion time n channels enabled, 1 n 8 l 450?n 500?n 550? n ns t acq acquisition time 8 channels enabled (t acq = t cyc C t conv C t busylh ) l 570 980 ns t cnvh cnv high time l 40 ns t cnvl cnv low time l 500 ns t busylh cnv to busy delay c l = 25pf l 30 ns t quiet digital i/o quiet time from cnv l 20 ns t pdh pd high time l 40 ns t pdl pd low time l 40 ns t wake refbuf wake-up time c refbuf = 47f, c refin = 0.1f 200 ms cmos i/o mode t scki scki period (notes 17, 18) l 10 ns t sckih scki high time l 4 ns t sckil scki low time l 4 ns t ssdiscki sdi setup time from scki (note 17) l 2 ns t hsdiscki sdi hold time from scki (note 17) l 1 ns t dsdoscki sdo data valid delay from scki c l = 25pf (note 17) l 7.5 ns t hsdoscki sdo remains valid delay from scki c l = 25pf (note 17) l 1.5 ns t skew sdo to scko skew (note 17) l C1 0 1 ns t dsdobusyl sdo data valid delay from busy c l = 25pf (note 17) l 0 ns t en bus enable time after cs (note 17) l 15 ns t dis bus relinquish time after cs (note 17) l 15 ns lvds i/o mode t scki scki period (note 19) l 4 ns t sckih scki high time (note 19) l 1.5 ns t sckil scki low time (note 19) l 1.5 ns t ssdiscki sdi setup time from scki (notes 11, 19) l 1.2 ns t hsdiscki sdi hold time from scki (notes 11, 19) l C0.2 ns t dsdoscki sdo data valid delay from scki (notes 11, 19) l 6 ns t hsdoscki sdo remains valid delay from scki (notes 11, 19) l 1 ns t skew sdo to scko skew (note 11) l C0.4 0 0.4 ns t dsdobusyl sdo data valid delay from busy (note 11) l 0 ns t en bus enable time after cs l 50 ns t dis bus relinquish time after cs l 15 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) ltc 2348-18 234818f
8 for more information www.linear.com/ltc2348-18 cmos timings 0.8 ? ov dd 0.2 ? ov dd 50% 50% 234818 f01 0.2 ? ov dd 0.8 ? ov dd 0.2 ? ov dd 0.8 ? ov dd t delay t width t delay lvds timings (differential) +200mv ?200mv 0v 0v 234818 f01b ?200mv +200mv ?200mv +200mv t delay t width t delay figure 1. voltage levels for timing specifications note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: v ddlbyp is the output of an internal voltage regulator, and should only be connected to a 2.2f ceramic capacitor to bypass the pin to gnd, as described in the pin functions section. do not connect this pin to any external circuitry. note 4: when these pin voltages are taken below v ee or above v cc , they will be clamped by internal diodes. this product can handle input currents of up to 100ma below v ee or above v cc without latch-up. note 5: when these pin voltages are taken below ground or above v dd or ov dd , they will be clamped by internal diodes. this product can handle currents of up to 100ma below ground or above v dd or ov dd without latch-up. note 6: C16.5v v ee 0v, 0v v cc 38v, 10v (v cc C v ee ) 38v, v dd? =?5v, unless otherwise specified. note 7: recommended operating conditions. note 8: exceeding these limits on any channel may corrupt conversion results on other channels. refer to absolute maximum ratings section for pin voltage limits related to device reliability. note 9: v cc = 15v, v ee = C15v, v dd = 5v, ov dd? =?2.5v, f smpl = 200ksps, internal reference and buffer, true bipolar input signal drive in bipolar softspan ranges, unipolar signal drive in unipolar softspan ranges, unless otherwise specified. note 10: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 11: guaranteed by design, not subject to test. note 12: for bipolar softspan ranges 7, 6, 3, and 2, zero-scale error is the offset voltage measured from C0.5lsb when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. full-scale error for these softspan ranges is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. for unipolar softspan ranges 5, 4, and 1, zero-scale error is the offset voltage measured from 0.5lsb when the output code flickers between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. full- scale error for these softspan ranges is the worst-case deviation of the last code transition from ideal and includes the effect of offset error. note 13: all specifications in db are referred to a full-scale input in the relevant softspan input range, except for crosstalk, which is referred to the crosstalk injection signal amplitude. note 14: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. note 15: when refbuf is overdriven, the internal reference buffer must be disabled by setting refin = 0v. note 16: i refbuf varies proportionally with sample rate and the number of active channels. note 17: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v, and ov dd = 5.25v. note 18: a t scki period of 10ns minimum allows a shift clock frequency of up to 100mhz for rising edge capture. note 19: v icm = 1.2v, v id = 350mv for lvds differential input pairs. a d c ti m ing c harac t eris t ics ltc 2348-18 234818f
9 for more information www.linear.com/ltc2348-18 typical p er f or m ance c harac t eris t ics integral nonlinearity vs output code and range integral nonlinearity vs output code and range integral nonlinearity vs output code and range integral nonlinearity vs output code dc histogram (zero-scale) dc histogram (near full-scale) integral nonlinearity vs output code and channel integral nonlinearity vs output code and channel differential nonlinearity vs output code and channel t a = 25c, v cc ?=?+15v, v ee ?=?C15v, v dd ?=?5v, ov dd ?=?2.5v, internal reference and buffer (v refbuf ?=?4.096v), f smpl = 200ksps, unless otherwise noted. 60000 70000 80000 90000 counts dc histogram (near full?scale) 234818 g09 true bipolar drive (in ? = 0v) 10.24v range arbitrary drive 234818 g07 ?1.5 ?1.0 ?0.5 0 0.5 1.0 in + /in ? common mode 1.5 swept ?10.24v to 10.24v 2.0 output code inl error (lsb) ?131072 vs output code ?65536 0 65536 131072 ?2.0 ?1.5 ltc 2348-18 234818f 10.24v range true bipolar drive (in ? = 0v) all channels output code ?131072 ?65536 0 65536 131072 ?2.0 integral nonlinearity 234818 g01 10.24v range fully differential drive (in ? = ?in + ) all channels output code ?131072 ?65536 ?1.0 0 ?0.5 65536 0 131072 0.5 ?2.0 1.0 1.5 2.0 inl error (lsb) vs output code integral nonlinearity ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 inl error (lsb) vs output code integral nonlinearity 234818 g02 all ranges all channels output code 0 65536 131072 196608 262144 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.0 0.1 0.2 0.3 0.4 0.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 inl error (lsb) vs output code integral nonlinearity dnl error (lsb) vs output code differential nonlinearity 234818 g03 10.24v and 10v ranges 5.12v and 5v ranges true bipolar drive (in ? = 0v ) one channel output code 234818 g05 unipolar drive (in ? = 0v ) one channel 0v to 5.12v range 0v to 10.24v and 0v to 10v ranges output code 0 65536 131072 ?131072 ?65536 0 65536 131072 ?2.0 ?1.5 ?1.0 ?0.5 0 196608 262144 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0.5 1.0 1.5 2.0 inl error (lsb) vs output code integral nonlinearity 234818 g04 10.24v, 10v, 5.12v, and 5v 2.0 inl error (lsb) vs output code integral nonlinearity 234818 g06 10.24v range = 1.3 code ?6 ?4 ?2 ranges fully differential drive (in ? = ?in + ) one channel output code ?131072 ?65536 0 65536 131072 ?2.0 ?1.5 0 2 4 6 0 10000 20000 30000 40000 50000 60000 70000 80000 90000 counts dc histogram (zero-scale) 234818 g08 10.24v range = 1.4 code 131056 131059 131062 131065 131068 0 10000 20000 30000 40000 50000
10 for more information www.linear.com/ltc2348-18 typical p er f or m ance c harac t eris t ics 32k point fft f smpl = 200khz, f in ?=?2khz snr, sinad vs v refbuf , f in ?=?2khz thd harmonics vs v refbuf , f in ?=?2khz snr, sinad vs input frequency thd, harmonics vs input frequency thd, harmonics vs input common mode, f in = 2khz 32k point fft f smpl ?=?200khz, f in ?=?2khz 32k point fft f smpl ?=?200khz, f in ?=?2khz 32k point arbitrary tw o -tone fft f smpl ?=?200khz, in + ?=?C7dbfs 2khz sine, in C ?=?C7dbfs 3.1khz sine t a = 25c, v cc ?=?+15v, v ee ?=?C15v, v dd ?=?5v, ov dd ?=?2.5v, internal reference and buffer (v refbuf ?=?4.096v), f smpl = 200ksps, unless otherwise noted. ?80 ?60 ?40 ?20 0 thd, harmonics (dbfs) common mode, f in = 2khz thd, harmonics vs input 234818 g18 true bipolar drive (in ? = 0v) 10.24v range thd 2nd 3rd frequency (hz) 40 100 60 1k 80 10k 100 100k ?180 ?130.0 ?160 10.24v range ?140 snr ?120 sinad ?100 frequency (hz) ?80 100 1k 10k 100k 78.0 82.0 ltc 2348-18 234818f snr = 96.7db thd = ?109db sinad = 96.5db sfdr = 110db 10.24v range true bipolar drive (in ? = 0v) frequency (khz) 0 ?120.0 20 ?110.0 ?100.0 ?90.0 ?80.0 ?60 ?70.0 ?40 thd, harmonics (dbfs) ?20 vs input frequency 0 thd, harmonics amplitude (dbfs) 234818 g17 f in = 2khz 86.0 32k point fft f smpl = 200khz, 90.0 234818 g10 94.0 snr = 96.7db 98.0 thd = ?119db 102.0 snr, sinad (dbfs) vs input frequency snr, sinad 234818 g16 true bipolar drive (in ? = 0v) sinad = 96.6db sfdr = 120db fully differential drive (in ? = ?in + ) 10.24v range frequency (khz) 0 20 40 60 80 100 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) f in = 2khz 32k point fft f smpl = 200khz, 234818 g11 sfdr = 119db 10.24v range arbitrary drive 6.2khz snr = 96.7db ?80 ?60 ?40 ?20 0 amplitude (dbfs) f in = 2khz 32k point fft f smpl = 200khz, 234818 g13 snr frequency (khz) 0 20 40 60 80 100 ?180 ?160 ?140 sinad refbuf voltage (v) 2.5 3 3.5 4 4.5 5 90.0 92.0 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) in ? = ?7dbfs 3.1khz sine 200khz, in + = ?7dbfs 2khz sine, 94.0 96.0 98.0 100.0 snr, sinad (dbfs) snr, sinad vs v refbuf , f in = 2khz 234818 g14 true bipolar drive (in ? = 0v) 2.5 ? v refbuf range true bipolar drive (in ? = 0v) 32k point two-tone fft f smpl = 234818 g12 snr = 93.2db thd = ?113db sinad = 93.2db sfdr = 114db true bipolar drive (in ? = 0v) 5.12v range frequency (khz) 0 2.5 ? v refbuf range thd 2nd 3rd refbuf voltage (v) 2.5 3 3.5 4 4.5 20 40 60 80 100 ?180 ?160 ?140 ?120 ?100 5 ?130.0 ?125.0 ?120.0 ?115.0 ?110.0 ?105.0 ?100.0 thd, harmonics (dbfs) f in = 2khz thd, harmonics vs v refbuf , 234818 g15 2nd thd 3rd 2v p-p fully differential drive ?14.5v v cm 10.5v 10.24v range input common mode (v) ?15 ?10 ?5 0 5 10 15 ?160 ?140 ?120 ?100
11 for more information www.linear.com/ltc2348-18 typical p er f or m ance c harac t eris t ics snr, sinad vs temperature, f in ?=?2khz thd, harmonics vs temperature, f in = 2khz inl/dnl vs temperature positive full-scale error vs temperature and channel negative full-scale error vs temperature and channel zero-scale error vs temperature and channel snr, sinad vs input level, f in ?=?2khz cmrr vs input frequency and channel crosstalk vs input frequency and channel t a = 25c, v cc ?=?+15v, v ee ?=?C15v, v dd ?=?5v, ov dd ?=?2.5v, internal reference and buffer (v refbuf ?=?4.096v), f smpl = 200ksps, unless otherwise noted. full?scale error (%) vs temperature positive full?scale error 234818 g25 10.24v range all channels temperature (c) ?55 ?35 ?15 10.24v range all channels 10.24v range all channels temperature (c) 96.0 ?55 96.5 ?35 97.0 ?15 97.5 5 98.0 25 snr, sinad (dbfs) 5 f in = 2khz 25 snr, sinad vs input level, 45 234818 g19 65 10.24v range true bipolar drive (in ? = 0v) 85 105 125 ?0.100 ?0.075 ?0.050 ltc 2348-18 234818f snr sinad input level (dbfs) ?40 ?30 ?20 ?10 45 0 65 85 105 125 in + = in ? = 18v p-p sine ?5 all channels ?4 frequency (hz) ?3 10 ?2 100 ?1 1k ?0.025 10k 0.000 100k 0.025 1m 0.050 65.0 0.075 0.100 full?scale error (%) vs temperature negative full?scale error 234818 g26 0 1 2 3 4 75.0 5 85.0 zero-scale error (lsb) 95.0 zero-scale error vs temperature 105.0 234818 g27 115.0 125.0 135.0 cmrr (db) cmrr vs input frequency 234818 g20 10.24v range ch2 ch1 in0 ? = 18v p-p sine all channels converting in0 + = 0v 10.24v range ch7 frequency (hz) 10 100 1k 10k 100k 1m ?135.0 ?130.0 ?125.0 ?120.0 ?115.0 ?110.0 ?55 ?35 ?15 5 25 45 65 85 105 125 ?105.0 ?100.0 ?95.0 ?90.0 ?85.0 ?80.0 crosstalk (db) crosstalk vs input frequency 234818 g21 snr ?125.0 ?120.0 ?115.0 ?110.0 ?105.0 ?100.0 ?95.0 thd, harmonics (dbfs) f in = 2khz thd, harmonics vs temperature, sinad temperature (c) ?55 ?35 ?15 5 25 45 65 85 234818 g23 10.24v range true bipolar drive (in ? = 0v) max inl min inl max dnl min dnl temperature (c) ?55 ?35 ?15 105 125 94.0 94.5 95.0 95.5 96.0 96.5 97.0 97.5 5 25 45 65 85 105 125 ?2.0 ?1.5 ?1.0 98.0 snr, sinad (dbfs) f in = 2khz snr, sinad vs temperature, 234818 g22 10.24v range true bipolar drive (in ? = 0v) thd 2nd 3rd temperature (c) ?0.5 0 0.5 1.0 1.5 2.0 inl, dnl error (lsb) inl/dnl vs temperature 234818 g24 10.24v range true bipolar drive (in ? = 0v) temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 ?0.100 ?0.075 ?0.050 ?0.025 0.000 0.025 0.050 0.075 0.100
12 for more information www.linear.com/ltc2348-18 typical p er f or m ance c harac t eris t ics internal reference output vs temperature supply current vs sampling rate step response (large-signal settling) step response (fine settling) supply current vs temperature power-down current vs temperature offset error vs input common mode t a = 25c, v cc ?=?+15v, v ee ?=?C15v, v dd ?=?5v, ov dd ?=?2.5v, internal reference and buffer (v refbuf ?=?4.096v), f smpl = 200ksps, unless otherwise noted. 400 sampling frequency (khz) 500 0 600 40 700 80 800 120 900 160 ?250 200 ?200 ?4 ?150 ?2 ?100 0 1 10 100 1000 power-down current (a) vs temperature power-down current 234818 g29 v cc = 21.5v, v ee = ?16.5v v cm = ?16.5v to 17.5v ?50 2 0 4 50 6 100 8 150 10 200 12 250 14 deviation from final value (lsb) 16 step response (fine settling) 18 234818 g34 supply current (ma) v cc = 38v, v ee = 0v v cm = 0v to 34v 10.24v range input common mode (v) ?16.5 0 17.5 34 ?2.0 ?1.5 supply current vs sampling rate 234818 g32 10.24v range in + = 200.0061khz square wave in ? = 0v settling time (ns) ?100 0 100 200 ?1.0 5 ?0.5 25 0 45 0.5 65 1.0 85 1.5 105 2.0 125 offset error (lsb) ?4 vs input common mode ?2 offset error 0 300 400 500 600 700 800 900 ?131072 ?98304 ?65536 234818 g30 2 15 units 4 temperature (c) 6 ?55 8 ?35 10 ?15 12 5 14 25 16 45 18 65 20 ?32768 0 32768 65536 98304 131072 output code (lsb) (large?signal settling) step response 234818 g33 85 supply current (ma) 105 supply current vs temperature 125 234818 g28 2.045 i ovdd 2.046 i vdd 2.047 ?i vee 2.048 i vcc 2.049 temperature (c) 2.050 ?55 2.051 ?35 10.24v range internal reference output (v) in + = 200.0061khz vs temperature square wave internal reference output in ? = 0v 234818 g31 settling time (ns) i ovdd ?100 i vdd 0 i vee 100 i vcc 200 with nap mode 300 t acq = 1s ?15 5 25 ltc 2348-18 45 234818f 65 i ovdd 85 i vdd 105 i vee 125 0.01 i vcc 0.1 temperature (c) ?55 ?35 ?15
13 for more information www.linear.com/ltc2348-18 p in func t ions pins that are the same for all digital i/o modes in0 + to in7 + , in0 ? to in7 ? (pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 47, and 48): positive and negative analog inputs, channels 0 to 7. the converter simultane - ously samples and digitizes (v in + C v in C) for all channels. wide input common mode range (v ee v cm v cc C 4v) and high common mode rejection allow the inputs to ac - cept a wide variety of signal swings. full-scale input range is determined by the channel s softspan configuration. gnd (pins 15, 18, 20, 30, 41, 44, 46): ground. solder all gnd pins to a solid ground plane. v cc (pin 16): positive high voltage power supply . the range of v cc is 0v to 38v with respect to gnd and 10v to 38v with respect to v ee . bypass v cc to gnd close to the pin with a 0.1f ceramic capacitor. in applications where v cc is shorted to gnd this capacitor may be omitted. v ee (pins 17, 45): negative high voltage power supply . the range of v ee is 0v to C16.5v with respect to gnd and C10v to C38v with respect to v cc . connect pins 17 and 45 together and bypass the v ee network to gnd close to pin 17 with a 0.1f ceramic capacitor. in applications where v ee is shorted to gnd this capacitor may be omitted. refin (pin 19): bandgap reference output/reference buffer input. an internal bandgap reference nominally outputs 2.048v on this pin. an internal reference buffer amplifies v refin to create the converter master reference voltage v refbuf = 2??? v refin on the refbuf pin. when using the internal reference, bypass refin to gnd (pin 20) close to the pin with a 0.1f ceramic capacitor to filter the bandgap output noise. if more accuracy is desired, overdrive refin with an external reference in the range of 1.25v to 2.2v. refbuf (pin 21): internal reference buffer output. an internal reference buffer amplifies v refin to create the converter master reference voltage v refbuf = 2??? v refin on this pin, nominally 4.096v when using the internal bandgap reference. bypass refbuf to gnd (pin 20) close to the pin with a 47f ceramic capacitor. the internal reference buffer may be disabled by grounding its input at refin. with the buffer disabled, overdrive refbuf with an ex - ternal reference voltage in the range of 2.5v to 5v. when using the internal reference buffer , limit the loading of any external circuitry connected to refbuf to less than 10a. using a high input impedance amplifier to buffer v refbuf to any external circuits is recommended. pd (pin 22): power down input. when this pin is brought high, the ltc2348-18 is powered down and subsequent conversion requests are ignored. if this occurs during a conversion, the device powers down once the conversion completes. if this pin is brought high twice without an intervening conversion , an internal global reset is initi - ated, equivalent to a power-on-reset event. logic levels are determined by ov dd . lvds / cmos ( pin 23): i / o mode select. tie this pin to ov dd to select lvds i /o mode, or to ground to select cmos i/o mode. logic levels are determined by ov dd . cnv (pin 24): conversion start input. a rising edge on this pin puts the internal sample-and-holds into the hold mode and initiates a new conversion. cnv is not gated by cs, allowing conversions to be initiated independent of the state of the serial i/o bus. busy (pin 38): busy output. the busy signal indicates that a conversion is in progress. this pin transitions low- to-high at the start of each conversion and stays high until the conversion is complete. logic levels are determined by ov dd . v ddlbyp (pin 40): internal 2.5v regulator bypass pin. the voltage on this pin is generated via an internal regulator operating off of v dd . this pin must be bypassed to gnd close to the pin with a 2.2f ceramic capacitor. do not connect this pin to any external circuitry. v dd (pins 42, 43): 5v power supply. the range of v dd is 4.75v to 5.25v. connect pins 42 and 43 together and bypass the v dd network to gnd with a shared 0.1f ceramic capacitor close to the pins. ltc 2348-18 234818f
14 for more information www.linear.com/ltc2348-18 p in func t ions cmos i/o mode sdo0 to sdo 7 (pins 25, 26, 27, 28, 33, 34, 35, and 36): cmos serial data outputs , channels 0 to 7. the most recent conversion result along with channel configuration information is clocked out onto the sdo pins on each ris - ing edge of scki. output data formatting is described in the digital inter face section . leave unused sdo outputs unconnected. logic levels are determined by ov dd . scki (pin 29): cmos serial clock input . drive scki with the serial i/o clock. scki rising edges latch serial data in on sdi and clock serial data out on sdo0 to sdo7. for standard spi bus operation , capture output data at the receiver on rising edges of scki. scki is allowed to idle either high or low. logic levels are determined by ov dd . ov dd (pin 31): i/ o interface power supply. in cmos i/o mode, the range of ov dd is 1.71v to 5.25v. bypass ov dd to gnd (pin 30) close to the pin with a 0.1f ceramic capacitor. scko (pin 32): cmos serial clock output. scki rising edges trigger transitions on scko that are skew-matched to the serial output data streams on sdo0 to sdo7. the resulting scko frequency is half that of scki. rising and falling edges of scko may be used to capture sdo data at the receiver (fpga) in double data rate (ddr) fashion. for standard spi bus operation, scko is not used and should be left unconnected. scko is forced low at the falling edge of busy. logic levels are determined by ov dd . sdi ( pin 37): cmos serial data input. drive this pin with the desired 24 - bit softspan configuration word ( see table ?1a ), latched on the rising edges of scki. if all channels will be configured to operate only in softspan 7, tie sdi to ov dd . logic levels are determined by ov dd . cs (pin 39): chip select input. the serial data i/o bus is enabled when cs is low and is disabled and hi-z when cs is high. cs also gates the external shift clock, scki. logic levels are determined by ov dd . lvds i/o mode sdo0, sdo 7 (pins 25 and 36): cmos serial data outputs. in lvds i/o mode, these pins are hi-z. sdi + , sdi C (pins 26 and 27): lvds positive and negative serial data input. differentially drive sdi + /sdi C with the desired 24- bit softspan configuration word ( see table 1a), latched on both the rising and falling edges of scki + / scki C . the sdi + /sdi C input pair is internally terminated with a 100 differential resistor when cs = 0. scki + , scki C ( pins 28 and 29): lvds positive and negative serial clock input. differentially drive scki + /scki C with the serial i /o clock. scki + /scki C rising and falling edges latch serial data in on sdi + /sdi C and clock serial data out on sdo + /sdo C . idle scki + /scki C low, including when transitioning cs. the scki + /scki C input pair is internally terminated with a 100 differential resistor when cs = 0. ov dd (pin 31): i/ o interface power supply. in lvds i/o mode, the range of ov dd is 2.375v to 5.25v. bypass ov dd to gnd (pin 30) close to the pin with a 0.1f ceramic capacitor. scko + , scko C (pins 32 and 33): lvds positive and negative serial clock output. scko + /scko C outputs a copy of the input serial i/o clock received on scki + /scki C , skew-matched with the serial output data stream on sdo + / sdo C . use the rising and falling edges of scko + /scko C to capture sdo + /sdo C data at the receiver (fpga). the scko + / scko C output pair must be differentially terminated with a 100 resistor at the receiver (fpga). sdo + , sdo C (pins 34 and 35): lvds positive and nega- tive serial data output . the most recent conversion result along with channel configuration information is clocked out onto sdo + /sdo C on both rising and falling edges of scki + /scki C , beginning with channel 0. the sdo + /sdo C output pair must be differentially terminated with a 100 resistor at the receiver (fpga). cs (pin 39): chip select input. the serial data i/o bus is enabled when cs is low, and is disabled and hi-z when cs is high. cs also gates the external shift clock, scki + / scki C . the internal 100 differential termination resistors on the scki + /scki C and sdi + /sdi C input pairs are disabled when cs is high. logic levels are determined by ov dd . ltc 2348-18 234818f
15 for more information www.linear.com/ltc2348-18 c on f igura t ion tables table 1a. softspan configuration table. use this table with table 1b to choose independent binary softspan codes ss[2:0] for each channel based on desired analog input range. combine softspan codes to form 24-bit softspan configuration word s[23:0]. use serial interface to write softspan configuration word to ltc2348-18, as shown in figure 19 binary softspan code ss[2:0] analog input range full scale range binar y format of conversion result 111 2.5 ? v refbuf 5 ? v refbuf tw o s complement 110 2.5 ? v refbuf /1.024 5 ? v refbuf /1.024 tw o s complement 101 0v to 2.5 ? v refbuf 2.5 ? v refbuf straight binary 100 0v to 2.5 ? v refbuf /1.024 2.5 ? v refbuf /1.024 straight binary 011 1.25 ? v refbuf 2.5 ? v refbuf tw o s complement 010 1.25 ? v refbuf /1.024 2.5 ? v refbuf /1.024 tw o s complement 001 0v to 1.25 ? v refbuf 1.25 ? v refbuf straight binary 000 channel disabled channel disabled all zeros table 1b. reference configuration table. the ltc2348-18 supports three reference configurations. analog input range scales with the converter master reference voltage, v refbuf reference configuration v refin v refbuf binary softspan code ss[2:0] analog input range internal reference with internal buffer 2.048 v 4.096v 111 10.24v 110 10v 101 0v to 10.24v 100 0v to 10v 011 5.12v 010 5v 001 0v to 5.12v external reference with internal buffer ( refin pin externally overdriven) 1.25v (min v alue) 2.5 v 111 6.25v 110 6.104v 101 0v to 6.25v 100 0v to 6.104v 011 3.125v 010 3.052v 001 0v to 3.125v 2.2v (max v alue) 4.4 v 111 11v 110 10.742v 101 0v to 11v 100 0v to 10.742v 011 5.5v 010 5.371v 001 0v to 5.5v ltc 2348-18 234818f
16 for more information www.linear.com/ltc2348-18 reference configuration v refin v refbuf binary softspan code ss[2:0] analog input range external reference unbuffered ( refbuf pin externally overdriven, refin pin grounded) 0 v 2.5v (min v alue) 111 6.25 v 110 6.104v 101 0v to 6.25v 100 0v to 6.104v 011 3.125v 010 3.052v 001 0v to 3.125v 0v 5v (max value) 111 12.5 v 110 12.207v 101 0v to 12.5v 100 0v to 12.207v 011 6.25v 010 6.104v 001 0v to 6.25v c on f igura t ion tables table 1b. reference configuration table (continued). the ltc2348-18 supports three reference configurations. analog input range scales with the converter master reference voltage, v refbuf ltc 2348-18 234818f
17 for more information www.linear.com/ltc2348-18 func t ional b lock diagra m sdo0 sdo7 scko sdi scki cs in0 + in0 ? busy 18-bit sar adc cmos serial i/o interface 234818 bd01 18 bits reference buffer refbuf refin gnd v cc v ee v ddlbyp v dd ov dd ltc2348-18 control logic 2.048v reference 2.5v regulator lvds/ cmos pdcnv s/h in1 + in1 ? s/h in2 + in2 ? s/h in3 + in3 ? s/h in4 + in4 ? s/h in5 + in5 ? s/h in6 + in6 ? s/h in7 + in7 ? s/h 8-channel multiplexer 20k 2 ? ? ? sdo + sdo ? scko + scko ? sdi + sdi ? scki + scki ? cs in0 + in0 ? busy 18-bit sar adc lvds serial i/o interface 234818 bd02 18 bits reference buffer refbuf refin gnd v cc v ee v ddlbyp v dd ov dd ltc2348-18 control logic 2.048v reference 2.5v regulator lvds/ cmos pdcnv s/h in1 + in1 ? s/h in2 + in2 ? s/h in3 + in3 ? s/h in4 + in4 ? s/h in5 + in5 ? s/h in6 + in6 ? s/h in7 + in7 ? s/h 8-channel multiplexer 20k 2 ltc 2348-18 234818f
18 for more information www.linear.com/ltc2348-18 ti m ing diagra m lvds i/o mode s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 2624 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3s4 s1s2 s0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ss1ss2 ss0 d17 d16 d15 cnv (cmos) cs = pd = 0 234818 td02 convert don?t care acquire busy (cmos) scko (lvds) sdo (lvds) scki (lvds) sdi (lvds) don?t care sample n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sample n + 1 softspan configuration word for conversion n + 1 channel 0 conversion n channel 1 conversion n channel 7 conversion n conversion result channel id softspan 186 187 188 189 190 191 192 d0 ss1ss2 ss0 d17 channel 0 conversion n conversion result channel id softspan c2 c1 c0 c2 c1 c0 cmos i/o mode s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3s4 s1s2 s0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c2 c1 c0 c2 c1 c0 ss1ss2 ss0 d17 cnv cs = pd = 0 convert don?t care acquire busy sdo7 scko sdo0 scki sdi don?t care sample n sample n + 1 softspan configuration word for conversion n + 1 channel 0 conversion n channel 1 conversion n channel 7 conversion n channel 0 conversion n 234818 td01 conversion result channel id softspan conversion result d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ss1ss2 ss0 d17 don?t care conversion result channel id softspan conversion result ? ? ? ltc 2348-18 234818f
19 for more information www.linear.com/ltc2348-18 a pplica t ions i n f or m a t ion o verview the ltc2348-18 is an 18-bit, low noise 8-channel si - multaneous sampling successive approximation register ( sar) adc with differential, wide common mode range inputs. the adc operates from a 5v low voltage supply and flexible high voltage supplies, nominally 15v. using the integrated low-drift reference and buffer (v refbuf? =?4.096 v nominal), each channel of this softspan adc can be in - dependently configured on a conversion-by-conversion basis to accept 10.24v, 0v to 10.24v, 5.12v, or 0v to 5.12v signals. the input signal range may be expanded up to 12.5v using an external 5v reference. individual channels may also be disabled to increase throughput on the remaining channels. the wide input common mode range and high cmrr (118db typical, v in + = v in C = 18v p-p 200hz sine) of the ltc2348- 18 analog inputs allow the adc to directly digitize a variety of signals, simplifying signal chain design. the absolute common mode input range is determined by the choice of high voltage supplies, which may be biased asymmetrically around ground and include the ability for either the positive or negative supply to be tied directly to ground. this input signal flexibility, combined with 3lsb inl, no missing codes at 18-bits, and 96.7db snr, makes the ltc2348-18 an ideal choice for many high voltage applications requiring wide dynamic range. the ltc2348-18 supports pin-selectable spi cmos (1.8v to 5v) and lvds serial interfaces , enabling it to com - municate equally well with legacy microcontrollers and modern fpgas . in cmos mode, applications may employ between one and eight lanes of serial output data, allowing the user to optimize bus width and data throughput. the ltc2348-18 typically dissipates 140mw when converting eight analog input channels simultaneously at 200ksps per channel throughput. optional nap and power down modes may be employed to further reduce power consumption during inactive periods. c onver ter o pera tion the ltc2348-18 operates in two phases. during the ac - quisition phase, the sampling capacitors in each channels sample-and-hold ( s/h) circuit connect to their respective analog input pins and track the differential analog input voltage (v in + C v in C). a rising edge on the cnv pin transi - tions all channels s/ h circuits from track mode to hold mode , simultaneously sampling the input signals on all channels and initiating a conversion. during the conversion phase, each channels sampling capacitors are connected, one channel at a time, to an 18-bit charge redistribution capacitor d/a converter (cdac). the cdac is sequenced through a successive approximation algorithm , effectively comparing the sampled input voltage with binary-weighted fractions of the channel s softspan full-scale range (e.g., v fsr /2, v fsr /4 v fsr /262144) using a differential comparator. at the end of this process, the cdac output approximates the channels sampled analog input. once all channels have been converted in this manner, the adc control logic prepares the 18-bit digital output codes from each channel for serial transfer. t ransfer f unction the ltc2348 - 18 digitizes each channel s full-scale voltage range into 2 18 levels. in conjunction with the adc master reference voltage, v refbuf , a channels softspan configu - ration determines its input voltage range, full-scale range, lsb size , and the binary format of its conversion result, as shown in tables 1a and 1b. for example, employing the internal reference and buffer (v refbuf = 4.096v nominal), softspan 7 configures a channel to accept a 10.24v bipolar analog input voltage range, which corresponds to a 20.48v full-scale range with a 78.125v lsb . other softspan configurations and reference voltages may be employed to convert both larger and smaller bipolar and unipolar input ranges . conversion results are output in two s complement binary format for all bipolar softspan ranges, and in straight binary format for all unipolar softspan ranges. the ideal twos complement transfer function is shown in figure 2, while the ideal straight binary transfer function is shown in figure 3. ltc 2348-18 234818f
20 for more information www.linear.com/ltc2348-18 input voltage (v) 0v output code (two?s complement) ?1 lsb 234818 f02 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 ? 1lsb ?fsr/2 fsr = +fs ? ?fs 1lsb = fsr/262144 figure 2. ltc2348-18 tw o s complement transfer function input voltage (v) output code (straight binary) 234818 f03 111...111 111...110 100...001 100...000 000...000 000...001 011...110 unipolar zero 011...111 fsr ? 1lsb 0v fsr = +fs 1lsb = fsr/262144 figure 3. ltc2348-18 straight binary transfer function a nalog i nputs each channel of the ltc2348 - 18 simultaneously samples the voltage difference (v in + C v in C) between its analog input pins over a wide common mode input range while attenuating unwanted signals common to both input pins by the common-mode rejection ratio ( cmrr) of the adc. wide common mode input range coupled with high cmrr allows the in + / in C analog inputs to swing with an arbitrary relationship to each other , provided each pin remains between (v cc C 4v) and v ee . this unique feature of the ltc2348- 18 enables it to accept a wide variety of signal swings, including traditional classes of analog input signals such as pseudo-differential unipolar, a pplica t ions i n f or m a t ion pseudo-differential true bipolar, and fully differential, simplifying signal chain design. the wide operating range of the high voltage supplies offers further input common mode flexibility. as long as the voltage difference limits of 10v v cc C v ee 38v are observed , v cc and v ee may be independently biased anywhere within their own individual allowed operating ranges, including the ability for either of the supplies to be tied directly to ground. this feature enables the common mode input range of the ltc2348-18 to be tailored to the specific applications requirements. in all softspan ranges, each channels analog inputs can be modeled by the equivalent circuit shown in figure 4. at the start of acquisition , the 40pf sampling capacitors (c in ) connect to the analog input pins in + /in C through the sampling switches, each of which has approximately 600 (r in ) of on-resistance. the initial voltage on both sampling capacitors at the start of acquisition is approximately equal to the sampled common-mode voltage (v in +?+?v in C)/2 from the prior conversion. the external circuitry connected to in + and in C must source or sink the charge that flows through r in as the sampling capacitors settle from their initial voltages to the new input pin voltages over the course of the acquisition interval . during conversion, nap, and power down modes, the analog inputs draw only a small leakage current. the diodes at the inputs provide esd protection. in + r in 600 r in 600 c in 40pf c in 40pf v cc v cc v ee v ee bias voltage in ? 234818 f04 figure 4. equivalent circuit for differential analog inputs, single channel shown ltc 2348-18 234818f
21 for more information www.linear.com/ltc2348-18 a pplica t ions i n f or m a t ion bipolar softspan input ranges for channels configured in softspan ranges 7, 6, 3, or 2, the ltc2348-18 digitizes the differential analog input voltage (v in + C v in C) over a bipolar span of 2.5??? v refbuf , 2.5??? v refbuf /1.024, 1.25??? v refbuf , or 1.25? ?? v refbuf /1.024, respectively, as shown in table 1a. these softspan ranges are useful for digitizing input signals where in + and in C swing above and below each other. traditional examples include fully differential input signals, where in + and in C are driven 180 degrees out-of- phase with respect to each other centered around a common mode voltage (v in +?+?v in C)/2, and pseudo-differential true bipolar input signals , where in + swings above and below a ground reference level, driven on in C . regardless of the chosen softspan range, the wide common mode input range and high cmrr of the in + /in C analog inputs allow them to swing with an arbitrary relationship to each other , provided each pin remains between (v cc C 4v) and v ee . the output data format for all bipolar softspan ranges is twos complement. unipolar softspan input ranges for channels configured in softspan ranges 5, 4, or 1, the ltc2348-18 digitizes the differential analog input voltage (v in + C v in C) over a unipolar span of 0v to 2.5??? v refbuf , 0v to 2.5??? v refbuf /1.024, or 0v to 1.25??? v refbuf , respectively, as shown in table 1a. these softspan ranges are useful for digitizing input signals where in + remains above in C . a traditional example includes pseudo-differential unipolar input signals, where in + swings above a ground reference level, driven on in C . regardless of the chosen softspan range, the wide common mode input range and high cmrr of the in + /in C analog inputs allow them to swing with an arbitrary relationship to each other , provided each pin remains between (v cc C 4v) and v ee . the output data format for all unipolar softspan ranges is straight binary . i nput d rive c ircuits the initial voltage on each channel s sampling capacitors at the start of acquisition must settle to the new input pin voltages during the acquisition interval . the external circuitry connected to in + and in C must source or sink the charge that flows through r in as this settling occurs. the ltc2348-18 sampling network rc time constant of 24ns implies an 18-bit settling time to a full-scale step of approximately 13???( r in ?? ? c in )?=?312ns. the impedance and self-settling of external circuitry connected to the analog input pins will increase the overall settling time required. low impedance sources can directly drive the inputs of the ltc2348-18 without gain error , but high impedance sources should be buffered to ensure sufficient settling during acquisition and to optimize the linearity and distor - tion performance of the adc . settling time is an important consideration even for dc input signals , as the voltages on the sampling capacitors will differ from the analog input pin voltages at the start of acquisition. most applications should use a buffer amplifier to drive the analog inputs of the ltc2348-18. the amplifier provides low output impedance, enabling fast settling of the analog signal during the acquisition phase. it also provides isola - tion between the signal source and the charge flow at the analog inputs when entering acquisition . input filtering the noise and distortion of an input buffer amplifier and other supporting cir cuitry must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier with a low- bandwidth filter to minimize noise. the simple one-pole rc lowpass filter shown in figure 5 is sufficient for many applications. at the output of the buffer , a lowpass rc filter network formed by the 600 sampling switch on-resistance (r in ) and the 40pf sampling capacitance (c in ) limits the input bandwidth on each channel to 7mhz, which is fast enough to allow for sufficient transient settling during acquisition ltc 2348-18 234818f
22 for more information www.linear.com/ltc2348-18 while simultaneously filtering driver wideband noise. a buffer amplifier with low noise density should be selected to minimize snr degradation over this bandwidth . an additional filter network may be placed between the buf - fer output and adc input to further minimize the noise contribution of the buffer and reduce disturbances to the buffer from adc acquisition transients . a simple one-pole lowpass rc filter is sufficient for many applications. it is important that the rc time constant of this filter be small enough to allow the analog inputs to completely settle to 18-bit resolution within the adc acquisition time (t acq ), as insufficient settling can limit inl and thd performance . high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo/cog and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self-heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. a pplica t ions i n f or m a t ion buffering arbitrary and fully differential analog input signals the wide common mode input range and high cmrr of the ltc2348-18 allow each channel s in + and in C pins to swing with an arbitrary relationship to each other , provided each pin remains between (v cc C 4v) and v ee . this unique feature of the ltc2348-18 enables it to accept a wide variety of signal swings, simplifying signal chain design. in many applications, connecting a channels in + and in C pins directly to the existing signal chain circuitry will not allow the channels sampling network to settle to 18-bit resolution within the adc acquisition time (t acq ). in these cases, it is recommended that two unity-gain buffers be inserted between the signal source and the adc input pins, as shown in figure 6a. table 2 lists several amplifier and lowpass filter combinations recommended for use in this circuit . the lt1469 combines fast settling, high linearity, and low offset with 5nv/hz input-referred noise density, enabling it to achieve the full adc data sheet snr and thd specifications, as shown in the fft plots in figures?6b to 6e. in applications where slightly degraded ltc2348-18 234818 f05 only channel 0 shown for clarity 0v true bipolar input signal in0 + in0 ? buffer amplifier lowpass signal filter 10nf 160 bw = 100khz figure 5. true bipolar signal chain with input filtering table 2. recommended amplifier and filter combinations for the buffer circuits in figures 6a and 9. ac performance measured using circuit in figure 6a, 10.24v range amplifier r filt () c filt (pf) input signal drive snr (db) thd (db) sinad (db) sfdr (db) ? lt1469 49.9 1000 fully differential 96.7 ?119 96.6 120 ? lt1355 100 270 fully differential 96.5 ?119 96.4 120 ? lt1469 49.9 1000 true bipolar 96.7 ?109 96.5 110 ? lt1355 100 270 true bipolar 96.5 ?106 96.1 108 ? lt1469 0 0 true bipolar 95.7 ?109 95.5 110 ? lt1355 0 0 true bipolar 95.9 ?106 95.5 108 ltc 2348-18 234818f
23 for more information www.linear.com/ltc2348-18 a pplica t ions i n f or m a t ion figure 6b. tw o - tone test. in + = C7dbfs 2 khz sine, in C = C7dbfs 3.1khz sine, 32 k point fft , f smpl = 200 ksps. circuit shown in figure 6 a with lt1469 amplifiers, r filt = 49.9, c filt = 1000pf figure 6c. in + / in C = C1dbfs 2 khz fully differential sine, v cm ?=?0v , 32 k point fft , f smpl = 200 ksps. circuit shown in figure 6 a with lt1469 amplifiers, r filt = 49.9, c filt = 1000pf ?15v ?15v 15v 15v ltc2348-18 234818 f06a only channel 0 shown for clarity +10v 0v ?10v fully differential +10v 0v ?10v true bipolar +10v 0v ?10v arbitrary +10v 0v ?10v unipolar ? + ? + 0.1f 0.1f 0.1f 47f in0 + in0 ? amplifier amplifier v cc refin refbuf v ee optional lowpass filters c filt c filt r filt r filt in + in ? figure 6a. buffering arbitrary, fully differential, true bipolar, and unipolar signals. see table 2 for recommended amplifier and filter combinations figure 6d. in + = C1dbfs 2khz true bipolar sine, in C = 0v, 32k point fft , f smpl = 200ksps. circuit shown in figure 6a with lt1469 amplifiers, r filt = 49.9, c filt = 1000pf figure 6e. in + = C1dbfs 2khz unipolar sine, in C = 0v, 32k point fft , f smpl = 200ksps. circuit shown in figure 6a with lt1469 amplifiers, r filt = 49.9, c filt = 1000pf 234818 f06c snr = 96.7db thd = ?109db sinad = 96.5db sfdr = 110db 10.24v range frequency (khz) 0 20 40 60 80 100 ?180 ?160 ?140 ?120 ?100 ?80 ?60 60 ?40 80 ?20 100 0 ?180 amplitude (dbfs) ?160 true bipolar drive ?140 234818 f06d ?120 snr = 90.8db ?100 thd = ?111db ?80 sinad = 90.7db ?60 sfdr = 112db ?40 0v to 10.24v range ?20 frequency (khz) 0 0 amplitude (dbfs) 20 arbitrary drive 40 234818 f06b 60 snr = 96.7db 80 thd = ?119db 100 sinad = 96.6db ?180 sfdr = 120db ?160 10.24v range ?140 frequency (khz) ?120 0 ?100 20 ?80 40 ?60 60 ?40 80 ?20 100 0 ?180 amplitude (dbfs) ?160 unipolar drive 234818 f06e ?140 ?120 ?100 ltc 2348-18 ?80 234818f ?60 sfdr = 119db ?40 10.24v range ?20 6.2khz 0 amplitude (dbfs) snr = 96.7db fully differential drive frequency (khz) 0 20 40
24 for more information www.linear.com/ltc2348-18 snr and thd performance is acceptable , it is possible to drive the ltc2348-18 using the lower-power lt1355. the lt1355 combines fast settling, good linearity, and moderate offset with 10nv/hz input-referred noise den - sity, enabling it to drive the ltc 2348-18 with only 0.2db snr loss and 3db thd loss compared with the lt1469. as shown in table ?2, both recommended amplifiers may be used without a lowpass filter at a loss of 1db snr due to increased wideband noise. the two-tone test shown in figure 6b demonstrates the arbitrary input drive capability of the ltc2348- 18. this test simultaneously drives in + with a ?7d bfs 2 khz single-ended sine wave and in ? with a ?7dbfs 3.1khz single-ended sine wave. together, these signals sweep the analog inputs across a wide range of common mode and differential mode voltage combinations, similar to the more general arbitrary input signal case . they also have a simple spec - tral representation. an ideal differential converter with no common-mode sensitivity will digitize this signal as two ? 7d bfs spectral tones, one at each sine wave frequency. the fft plot in figure 6b demonstrates the ltc2348-18 response approaches this ideal, with 119db of sfdr limited by the converter 's second harmonic distortion response to the 3.1khz sine wave on in C . the ability of the ltc2348-18 to accept arbitrary signal swings over a wide input common mode range with high cmrr can simplify application solutions. in practice, many sensors produce a differential sensor voltage riding on top of a large common mode signal. figure 7a depicts one way of using the ltc2348-18 to digitize signals of this type. the amplifier stage provides a differential gain of approximately 10v/v to the desired sensor signal while the unwanted common mode signal is attenuated by the adc cmrr . the circuit employs the 5v softspan range of the adc. figure ?7b shows measured cmrr performance of this solution, which is competitive with the best com - mercially available instrumentation amplifiers . figure ?7 c shows measured ac per formance of this solution. in figure 8, another application circuit is shown which uses two channels of the ltc2348-18 to simultaneously sense the voltage on and bidirectional current through a sense resistor over a wide common mode range. in many applica - tions of this type, the impedance of the external circuitry is low enough that the adc sampling network can fully settle without buffering. ?5v ?5v 31v 31v ltc2348-18 234818 f07a only channel 0 shown for clarity 24v 0v arbitrary + ? + ? 0.1f 0.1f 0.1f 47f in0 + in0 ? ? lt1124 ? lt1124 v cc refin refbuf v ee lowpass filters bw ~ 500khz 6.6nf 6.6nf 49.9 49.9 549 18pf 18pf in + in ? 2.49k 2.49k common mode input range differential mode input range: 500mv figure 7a. digitize differential signals over a wide common mode range a pplica t ions i n f or m a t ion ltc 2348-18 234818f
25 for more information www.linear.com/ltc2348-18 figure 7b. cmrr vs input frequency. circuit shown in figure 7a figure 7c. in + / in C ?=?450mv 2khz fully differential sine, 0v??v cm ??24v, 32k point fft , f smpl = 100ksps. circuit shown in figure 7a ?15v 15v ltc2348-18 234818 f08 only channels 0 and 1 shown for clarity 0.1f 0.1f 0.1f 47f ?10.24v v s1 10.24v ?10.24v v s2 10.24v v s1 ? v s2 r sense i sense = in0 + in0 ? in1 + in1 ? v cc refin refbuf v ee i sense r sense v s2 v s1 figure 8. simultaneously sense voltage (ch0) and current (ch1) over a wide common mode range buffering single-ended analog input signals while the circuit shown in figure 6a is capable of buffering single-ended input signals, the circuit shown in figure 9 is preferable when the single-ended signal reference level is inherently low impedance and doesn't require buffering. this circuit eliminates one driver and lowpass filter , reduc - ing part count, power dissipation, and snr degradation due to driver noise . using the recommended driver and filter combinations in table 2, the performance of this circuit with single-ended input signals is on par with the performance of the circuit in figure 6a. ?15v ?15v 15v 15v ltc2348-18 234818 f09 only channel 0 shown for clarity true bipolar +10v 0v ?10v +10v 0v ?10v unipolar ? + 0.1f 0.1f 0.1f 47f in0 + in0 ? amplifier v cc refin refbuf v ee optional lowpass filter c filt r filt in + in ? figure 9. buffering single-ended input signals. see table 2 for recommended amplifier and filter combinations a pplica t ions i n f or m a t ion 10k 100k 50 60 70 80 90 100 110 120 cmrr (db) cmrr vs input frequency 234818 f07b snr = 89.8db thd = ?116db sinad = 89.8db sfdr = 119db fully differential drive (in ? = ?in + ) 5v range frequency (khz) 0 10 20 30 40 50 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ltc 2348-18 ?40 234818f ?20 5v range 0 in + = in ? = 1v p?p sine amplitude (dbfs) in + = in ? = 24v p?p sine 234818 f07c op?amps slew f in > 30khz frequency (hz) 10 100 1k
26 for more information www.linear.com/ltc2348-18 adc r eference as shown previously in table 1b, the ltc2348-18 supports three reference configurations. the first uses both the in - ternal bandgap reference and reference buffer. the second externally overdrives the internal reference but retains the internal buffer, which isolates the external reference from adc conversion transients. this configuration is ideal for sharing a single precision external reference across multiple adcs . the third disables the internal buffer and overdrives the refbuf pin externally. internal reference with internal buffer the ltc2348-18 has an on-chip, low noise, low drift (20ppm/c maximum), temperature compensated band - gap reference that is factory trimmed to 2.048v. the reference output connects through a 20k resistor to the refin pin, which serves as the input to the on-chip reference buffer, as shown in figure 10a. when employing the internal bandgap reference , the refin pin should be bypassed to gnd (pin 20) close to the pin with a 0.1f ceramic capacitor to filter wideband noise. the reference buffer amplifies v refin to create the converter master reference voltage v refbuf = 2??? v refin on the refbuf pin, nominally 4.096v when using the internal bandgap refer - ence. bypass refbuf to gnd (pin 20) close to the pin with at least a 47f ceramic capacitor (x7r, 10v, 1210 size or x5r, 10v, 0805 size) to compensate the reference buffer, absorb transient conversion currents , and minimize noise. 234818 f10a 47f 6.5k 20k ltc2348-18 reference buffer refbuf refin gnd bandgap reference 6.5k 0.1f figure 10a. internal reference with internal buffer configuration external reference with internal buffer if more accuracy and/or lower drift is desired, refin can be easily overdriven by an external reference since 20k of resistance separates the internal bandgap reference output from the refin pin, as shown in figure 10b. the valid range of external reference voltage overdrive on the refin pin is 1.25v to 2.2v, resulting in converter mas - ter reference voltages v refbuf between 2.5v and 4.4v, respectively. linear technology offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power, and high accuracy, the ltc6655- 2.048 is well suited for use with the ltc2348-18 when overdriving the internal reference. the ltc6655 - 2.048 offers 0.025% ( maximum ) initial accuracy a pplica t ions i n f or m a t ion 234818 f10b 47f 6.5k 20k ltc2348-18 reference buffer refbuf refin gnd bandgap reference 6.5k 2.7f ltc6655-2.048 figure 10b. external reference with internal buffer configuration ltc 2348-18 234818f
27 for more information www.linear.com/ltc2348-18 and 2ppm/c (maximum) temperature coefficient for high precision applications. the ltc6655-2.048 is fully speci- fied over the h-grade temperature range, complementing the extended temperature range of the ltc2348-18 up to 125 c. bypassing the ltc6655- 2.048 with a 2.7f to 100f ceramic capacitor close to the refin pin is recommended. external reference with disabled internal buffer the internal reference buffer supports v refbuf = 4.4v maximum. by grounding refin, the internal buffer may be disabled allowing refbuf to be overdriven with an external reference voltage between 2.5v and 5v, as shown in figure 10c. maximum input signal swing and snr are achieved by overdriving refbuf using an external 5v reference. the buffer feedback resistors load the refbuf pin with 13k even when the reference buffer is disabled. the ltc6655-5 offers the same small size , accuracy, drift, and extended temperature range as the ltc6655-2.048, and achieves a typical snr of 97.5db when paired with the ltc2348-18. bypass the ltc6655-5 to gnd (pin 20) close to the refbuf pin with at least a 47f ceramic ca - pacitor ( x7r, 10v, 1210 size or x 5r, 10v, 0805 size) to absorb transient conversion currents and minimize noise . the ltc2348-18 converter draws a charge (q conv ) from the refbuf pin during each conversion cycle . on short time scales most of this charge is supplied by the external refbuf bypass capacitor, but on longer time scales all of the charge is supplied by either the reference buffer, or when the internal reference buffer is disabled, the external reference. this charge draw corresponds to a dc current equivalent of i refbuf = q conv ?? ? f smpl , which is proportional to sample rate. in applications where a burst of samples is taken after idling for long periods of time, as shown in figure?11, i refbuf quickly transitions from approximately 0.4ma to 1.5ma (v refbuf = 5v, f smpl ?=?200khz). this current step triggers a transient response in the external reference that must be considered, since any deviation in v refbuf affects converter accuracy. if an external reference is used to overdrive refbuf, the fast settling ltc6655 family of references is recommended. internal reference buffer transient response for optimum performance in applications employing burst sampling, the external reference with internal reference buffer configuration should be used. the internal reference buffer incorporates a proprietary design that minimizes movements in v refbuf when responding to a burst of conversions following an idle period. figure 12 compares a pplica t ions i n f or m a t ion cnv idle period idle period 234818 f11 figure 11. cnv waveform showing burst sampling 234818 f10c 47f 6.5k 20k ltc2348-18 reference buffer refbuf refin gnd bandgap reference 6.5k ltc6655-5 figure 10c. external reference with disabled internal buffer configuration ltc 2348-18 234818f
28 for more information www.linear.com/ltc2348-18 the burst conversion response of the ltc2348-18 with an input near full scale for two reference configurations. the first configuration employs the internal reference buffer with refin externally overdriven by an ltc6655-2.048, while the second configuration disables the internal ref - erence buffer and overdrives refbuf with an external ltc 6655-4.096. in both cases refbuf is bypassed to gnd with a 47f ceramic capacitor. figure 12. burst conversion response of the ltc2348-18, f smpl? =?200ksps d ynamic p erformance fast fourier transform ( fft ) techniques are used to test the adcs frequency response, distortion, and noise at the rated throughput . by applying a low distortion sine wave and analyzing the digital output using an fft algorithm , the adcs spectral content can be examined for frequen - cies outside the fundamental. the ltc2348-18 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies below half the sampling frequency, exclud - ing dc. figure 13 shows that the ltc2348-18 achieves a typical sinad of 96.5db in the 10.24v range at a 200khz sampling rate with a true bipolar 2khz input signal. signal-to-noise ratio (snr) the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc . figure 13 shows that the ltc2348-18 achieves a typical snr of 96.7db in the 10.24v range at a 200khz sampling rate with a true bipolar 2khz input signal. total harmonic distortion (thd) total harmonic distortion ( thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v 2 2 + v 3 2 + v 4 2 ...v n 2 v 1 where v 1 is the rms amplitude of the fundamental fre - quency and v 2 through v n are the amplitudes of the second through nth harmonics, respectively. figure 13 shows that the ltc2348-18 achieves a typical thd of C109db (n?=?6) in the 10.24v range at a 200khz sampling rate with a true bipolar 2khz input signal. figure 13. 32k point fft f smpl = 200ksps, f in = 2khz a pplica t ions i n f or m a t ion 200 300 400 500 ?5 0 5 10 15 20 deviation from final value (lsb) 234818 f12 snr = 96.7db thd = ?109db sinad = 96.5db sfdr = 110db true bipolar drive (in ? = 0v) 10.24v range frequency (khz) 0 20 40 60 80 100 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ltc 2348-18 ?20 234818f 0 internal reference buffer amplitude (dbfs) external reference on refbuf 234818 f13 in ? = 0v in + = 10v 10.24v range time (s) 0 100
29 for more information www.linear.com/ltc2348-18 p ower c onsiderations the ltc2348-18 provides four sets of power supply pins: the positive and negative high voltage power supplies (v cc and v ee ), the 5v core power supply (v dd ) and the digital input/output (i/o) interface power supply (ov dd ). as long as the voltage difference limits of 10v v cc C v ee 38v are observed , v cc and v ee may be independently biased anywhere within their own individual allowed operating ranges, including the ability for either of the supplies to be tied directly to ground. this feature enables the common mode input range of the ltc2348-18 to be tailored to the specific application s requirements. the flexible ov dd sup - ply allows the ltc2348-18 to communicate with cmos logic operating between 1.8v and 5v, including 2.5v and 3.3v systems. when using lvds i/o mode, the range of ov dd is 2.375v to 5.25v. power supply sequencing the ltc2348-18 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2348-18 has an internal power-on-reset (por) circuit which resets the converter on initial power-up and whenever v dd drops below 2v. once the supply voltage re-enters the nominal supply voltage range , the por reinitializes the adc. no conversions should be initiated until at least 10ms after a por event to ensure the initialization period has ended. when employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the refbuf bypass capacitor. any conversion initiated before these times will produce invalid results. t iming and c ontrol cnv t iming the ltc2348 - 18 sampling and conversion is controlled by cnv. a rising edge on cnv transitions all channels s/h circuits from track mode to hold mode , simultaneously sampling the input signals on all channels and initiating a conversion. once a conversion has been started, it cannot be terminated early except by resetting the adc , as discussed in the reset timing section . for optimum performance, drive cnv with a clean, low jitter signal and avoid transitions on data i/o lines leading up to the rising edge of cnv . additionally , to minimize channel-to-channel crosstalk, avoid high slew rates on the analog inputs for 100ns before and after the rising edge of cnv. converter status is indicated by the busy output , which transitions low-to-high at the start of each conversion and stays high until the conversion is complete. once cnv is brought high to begin a conversion, it should be returned low between 40ns and 60ns later or after the falling edge of busy to minimize external disturbances during the internal conver - sion process. the cnv timing required to take advantage of the reduced power nap mode of operation is described in the nap mode section . internal conversion clock the ltc2348-18 has an internal clock that is trimmed to achieve a maximum conversion time of 550?n ns with n channels enabled. with a minimum acquisition time of 570ns, throughput performance of 200ksps is guaranteed without any external adjustments. a pplica t ions i n f or m a t ion cnv t conv t acq busy nap nap mode t cnvl 234818 f14 figure 14. nap mode timing for the ltc2348-18 ltc 2348-18 234818f
30 for more information www.linear.com/ltc2348-18 nap mode the ltc2348-18 can be placed into nap mode after a con - version has been completed to reduce power consumption between conversions . in this mode a portion of the device circuitry is turned off , including circuits associated with sampling the analog input signals . nap mode is enabled by keeping cnv high between conversions , as shown in figure 14. to initiate a new conversion after entering nap mode, bring cnv low and hold for at least 500ns before bringing it high again. the converter acquisition time (t acq ) is set by the cnv low time (t cnvl ) when using nap mode. power down mode when pd is brought high, the ltc2348-18 is powered down and subsequent conversion requests are ignored. if this occurs during a conversion, the device powers down once the conversion completes. in this mode, the device draws only a small regulator standby current resulting in a typical power dissipation of 0.36mw. to exit power down mode, bring the pd pin low and wait at least 10ms before initiating a conversion. when employing the internal refer - ence buffer, allow 200ms for the buffer to power up and recharge the refbuf bypass capacitor . any conversion initiated before these times will produce invalid results. reset timing a global reset of the ltc2348- 18, equivalent to a power- on-reset event, may be executed without needing to cycle the supplies. this feature is useful when recovering from system-level events that require the state of the entire sys - tem to be reset to a known synchronized value. t o initiate a global reset, bring pd high twice without an intervening conversion, as shown in figure 15. the reset event is trig - gered on the second rising edge of pd, and asynchronously a pplica t ions i n f or m a t ion ends based on an internal timer. reset clears all serial data output registers and restores the internal softspan configu - ration register default state of all channels in softspan ?7. if reset is triggered during a conversion , the conversion is immediately halted. the normal power down behavior associated with pd going high is not affected by reset. once pd is brought low , wait at least 10ms before initiating a conversion. when employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the refbuf bypass capacitor. any conversion initiated before these times will produce invalid results. power dissipation vs sampling frequency when nap mode is employed, the power dissipation of the ltc2348-18 decreases as the sampling frequency is reduced, as shown in figure 16. this decrease in aver - age power dissipation occurs because a portion of the ltc 2348-18 circuitry is turned off during nap mode , and the fraction of the conversion cycle (t cyc ) spent napping increases as the sampling frequency (f smpl ) is decreased. figure 16. power dissipation of the ltc2348-18 decreases with decreasing sampling frequency cnv t conv t cnvh t pdh t pdl busy reset reset time set internally second rising edge of pd triggers reset pd t wake 234818 f15 figure 15. reset timing for the ltc2348-18 40 80 120 160 200 ?4 ?2 0 2 4 6 8 10 12 14 16 18 supply current (ma) 234818 f16 ltc 2348-18 234818f i ovdd i vdd i vee i vcc with nap mode t acq = 1s sampling frequency (khz) 0
31 for more information www.linear.com/ltc2348-18 a pplica t ions i n f or m a t ion d igital i nterface the ltc2348 - 18 features cmos and lvds serial interfaces, selectable using the lvds /cmos pin. the flexible ov dd supply allows the ltc2348-18 to communicate with any cmos logic operating between 1.8v and 5v, including 2.5v and 3.3v systems, while the lvds interface supports low noise digital designs. in cmos mode, applications may employ between one and eight lanes of serial data output, allowing the user to optimize bus width and data throughput. together, these i/ o interface options enable the ltc2348-18 to communicate equally well with legacy microcontrollers and modern fpgas. serial cmos i/o mode as shown in figure 17, in cmos i/ o mode the serial data bus consists of a serial clock input, scki, serial data input, sdi, serial clock output, scko, and eight lanes of serial data output, sdo0 to sdo7. communication with the ltc2348-18 across this bus occurs during predefined data transaction windows. within a window, the device accepts 24- bit softspan configuration words for the next conversion on sdi and outputs 24-bit packets containing conversion results and channel configuration information from the previous conversion on sdo0 to sdo7. new data transaction windows open 10ms after powering up or resetting the ltc2348-18, and at the end of each con - version on the falling edge of busy. in the recommended use case, the data transaction should be completed with a minimum t quiet time of 20ns prior to the start of the next conversion, as shown in figure 17. new softspan configuration words are only accepted within this recom - mended data transaction window, but softspan changes take effect immediately with no additional analog input settling time required before starting the next conversion . it is still possible to read conversion data after starting the next conversion, but this will degrade conversion accuracy and therefore is not recommended. c2 c1 c0 c2 c1 c0 s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3s4 s1s2 s0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ss1ss2 ss0 d17 cnv cs = pd = 0 don?t care t acq busy sdo7 scko sdo0 scki sdi don?t care sample n recommended data transaction window sample n + 1 softspan configuration word for conversion n + 1 channel 0 24-bit packet conversion n channel 1 24-bit packet conversion n channel 7 24-bit packet conversion n channel 0 24-bit packet conversion n 234818 td01 conversion result channel id softspan conversion result d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ss1ss2 ss0 d17 don?t care conversion result channel id softspan conversion result ? ? ? t scki t sckih t busylh t sckil t hsdoscki t dsdoscki t ssdiscki t quiet t hsdiscki t dsdobusyl t cnvh t skew t conv t cnvl t cyc figure 17. serial cmos i/o mode ltc 2348-18 234818f
32 for more information www.linear.com/ltc2348-18 just prior to the falling edge of busy and the opening of a new data transaction window, scko is forced low and sdo0 to sdo7 are updated with the latest conversion results from analog input channels 0 to 7, respectively. rising edges on scki serially clock conversion results and analog input channel configuration information out on sdo0 to sdo7 and trigger transitions on scko that are skew-matched to the data on sdo0 to sdo7. the resulting scko frequency is half that of scki. scki rising edges also latch softspan configuration words provided on sdi, which are used to program the internal 24-bit softspan configuration register. see the section programming the softspan configuration register in cmos i/o mode for further details. scki is allowed to idle either high or low in cmos i/o mode. as shown in figure 18, the cmos bus is enabled when cs is low and is disabled and hi-z when cs is high, allowing the bus to be shared across multiple devices. the data on sdo0 to sdo7 are grouped into 24-bit packets consisting of an 18- bit conversion result , 3-bit analog channel id, and 3-bit softspan code, all presented msb first. as suggested in figures 17 and 18, each sdo lane outputs these packets for all analog input channels in a sequential, circular manner. for example, the first 24-bit packet output on sdo0 corresponds to analog input channel 0, followed by the packets for channels 1 through 7. the data output on sdo0 then wraps back to channel 0, and this pattern repeats indefinitely. other sdo lanes follow a similar circular pattern , except the first packet presented on each lane corresponds to its associated analog input channel. when interfacing the ltc2348-18 with a standard spi bus, capture output data at the receiver on rising edges of scki. scko is not used in this case. multiple sdo lanes are also usually not useful in this case. in other applica - tions, such as interfacing the ltc2348-18 with an fpga or cpld , rising and falling edges of scko may be used to capture serial output data on sdo0 to sdo7 in double data rate (ddr) fashion. capturing data using scko adds robustness to delay variations over temperature and supply. full eight lane serial cmos output data capture as shown in table 3, full 200ksps per channel throughput can be achieved with a 45mhz scki frequency by capturing the first packet (24 scki cycles total) from all eight serial data output lanes sdo 0 to sdo7. this configuration also allows conversion results from all channels to be captured using as few as 18 scki cycles if the 3-bit analog channel id and 3- bit softspan code are not needed and the device softspan configuration is not being changed. multi-lane data capture is usually best suited for use with fpga or cpld capture hardware, but may be useful in other application-specific cases. a pplica t ions i n f or m a t ion cs pd = 0 don?t care busy sdo7 scko sdo0 scki sdi don?t care don?t care don?t care 234818 f18 hi-z hi-z channel 0 packet channel 1 packet channel 2 packet channel 3 packet (partial) hi-z hi-z hi-z hi-z channel 7 packet channel 0 packet channel 1 packet channel 2 packet (partial) ? ? ? new softspan configuration word (overwrites internal config register) two all-zero words and one partial word (internal config register retains current value) t en t dis figure 18. internal softspan configuration register behavior. serial cmos bus response to cs ltc 2348-18 234818f
33 for more information www.linear.com/ltc2348-18 fewer than eight lane serial cmos output data capture applications that cannot accommodate the full eight lanes of serial data capture may employ fewer lanes without reconfiguring the ltc2348-18. for example, capturing the first two packets (48 scki cycles total) from sdo0, sdo2, sdo4, and sdo6 provides data for analog input channels 0 and 1, 2 and 3, 4 and 5, and 6 and 7, respec - tively, u sing four output lanes . similarly , capturing the first four packets (96 scki cycles total) from sdo0 and sdo4 provides data for analog input channels 0 to 3 and 4 to 7, respectively, using two output lanes. if only one lane can be accommodated, capturing the first eight packets (192 scki cycles total) from sdo0 provides data for all analog input channels . as shown in table 3, full 200ksps per channel throughput can be achieved with a 90mhz scki frequency in the four lane case, but the maximum cmos scki frequency of 100mhz limits the throughput to less than 200ksps per channel in the two lane and one lane cases . finally, note that in choosing the number of lanes and which lanes to use for data capture, the user is not restricted to the specific cases mentioned above . other choices may be more optimal in particular applications. programming the softspan configuration register in cmos i/o mode the internal 24-bit softspan configuration register con - trols the softspan range for all analog input channels of the ltc2348-18. the default state of this register after power-up or resetting the device is all ones , configuring each channel to convert in softspan 7, the 2.5 ? v refbuf range ( see table 1a). the state of this register may be modified by providing a new 24- bit softspan configuration word on sdi during the data transaction window shown in figure 17. new softspan configuration words are only accepted within this recommended data transaction win - dow, but softspan changes take effect immediately with no additional analog input settling time required before starting the next conversion. setting a channels softspan code to ss [2:0] = 000 immediately disables the channel, resulting in a corresponding reduction in t conv on the next conversion. similarly, enabling a previously disabled chan - nel requires no additional analog input settling time before starting the next conversion . the mapping between the serial softspan configuration word, the internal softspan configuration register, and each channel s 3-bit softspan code is illustrated in figure 19. if fewer than 24 scki rising edges are provided during a data transaction window, the partial word received on sdi will be ignored and the softspan configuration register will not be updated. if exactly 24 scki rising edges are provided, the softspan configuration register will be updated to match the received softspan configuration word, s[23:0]. the one exception to this behavior occurs when s[23:0] is all zeros . in this case, the softspan configuration register will not be updated , allowing applications to retain the current softspan configuration state by idling sdi low. if more than 24 scki rising edges are provided during a data transaction window, each complete 24-bit word received on sdi will be interpreted as a new softspan configuration word and applied to the softspan configuration register as described above. any partial words are ignored. a pplica t ions i n f or m a t ion table 3. required scki frequency to achieve various throughputs in common output bus configurations. shaded entries denote throughputs that are not achievable in a given configuration i/o mode number of sdo lanes number of scki cycles required f scki (mhz) to achieve throughput of 200ksps/channel 100ksps/channel 50ksps/channel cmos 8 18 35 4 2 8 24 45 5 2 4 48 90 9 4 2 96 not achievable 18 7 1 192 not achievable 35 13 lvds 1 96 180 (360mbps) 18 (36mbps) 7 (14mbps) ltc 2348-18 234818f
34 for more information www.linear.com/ltc2348-18 typically, applications will update the softspan configura - tion register in the manner shown in figures 17 and 18. after the opening of a new data transaction window at the falling edge of busy , the user supplies a 24-bit softspan configuration word on sdi during the first 24 scki cycles. this new word overwrites the internal configuration register contents following the 24th scki rising edge. the user then holds sdi low for the remainder of the data transaction window causing the register to retain its contents regardless of the number of additional scki cycles applied. softspan settings may be retained across multiple conversions by holding sdi low for the entire data transaction window, regardless of the number of scki cycles applied. serial lvds i/o mode in lvds i / o mode, information is transmitted using posi - tive and negative signal pairs (lvds + /lvds ? ) with bits differentially encoded as (lvds + ? lvds ? ). these signals are typically routed using differential transmission lines with 100 characteristic impedance. logical 1s and 0s are nominally represented by differential +350mv and ? 350mv, respectively. for clarity, all lvds timing diagrams and interface discussions adopt the logical rather than physical convention. as shown in figure 20, in lvds i/o mode the serial data bus consists of a serial clock differential input, scki, serial data differential input, sdi, serial clock differential output, scko, and serial data differential output, sdo. communi - cation with the ltc2348-18 across this bus occurs during predefined data transaction windows . within a window, the device accepts 24-bit softspan configuration words for the next conversion on sdi and outputs 24-bit packets containing conversion results and channel configuration information from the previous conversion on sdo. new data transaction windows open 10ms after powering up or resetting the ltc2348-18, and at the end of each con - version on the falling edge of busy. in the recommended use case , the data transaction should be completed with a minimum t quiet time of 20ns prior to the start of the next conversion, as shown in figure 20. new softspan configuration words are only accepted within this recom - mended data transaction window, but softspan changes s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3s4 s1s2 s0 don?t care scki sdi softspan configuration word cmos i/o mode softspan configuration word internal 24-bit softspan configuration register (same for cmos and lvds) lvds i/o mode 123456789 10111213141516171819202122 23 0 t scki s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3s4 s1s2 s0 don?t care scki (lvds) sdi (lvds) t scki channel 7 softspan code ss[2:0] channel 6 softspan code ss[2:0] channel 5 softspan code ss[2:0] channel 4 softspan code ss[2:0] channel 3 softspan code ss[2:0] channel 2 softspan code ss[2:0] channel 1 softspan code ss[2:0] channel 0 softspan code ss[2:0] 234818 f19 t sckih t sckil t ssdiscki t hsdiscki t sckih t sckil t hsdiscki t hsdiscki t ssdiscki t ssdiscki figure 19. mapping between serial softspan configuration word, internal softspan configuration register, and softspan code for each analog input channel a pplica t ions i n f or m a t ion ltc 2348-18 234818f
35 for more information www.linear.com/ltc2348-18 take effect immediately with no additional analog input settling time required before starting the next conversion. it is still possible to read conversion data after starting the next conversion, but this will degrade conversion accuracy and therefore is not recommended. just prior to the falling edge of busy and the opening of a new data transaction window, sdo is updated with the latest conversion results from analog input channel 0. both rising and falling edges on scki serially clock conversion results and analog input channel configuration information out on sdo. scki is also echoed on scko, skew-matched to the data on sdo. whenever possible, it is recommended that rising and falling edges of scko be used to capture ddr serial output data on sdo, as this will yield the best robustness to delay variations over supply and tempera - ture. scki rising and falling edges also latch softspan configuration words provided on sdi, which are used to program the internal 24- bit softspan configuration register. see the section programming the softspan configuration register in lvds i /o mode for further details. as shown in figure 21, the lvds bus is enabled when cs is low and is disabled and hi-z when cs is high, allowing the bus to be shared across multiple devices . due to the high speeds involved in lvds signaling , lvds bus sharing must be carefully considered. transmission line limitations imposed by the shared bus may limit the maximum achievable bus clock speed. lvds inputs are internally terminated with a 100 differential resistor when cs ?=?0, while outputs must be differentially terminated with a 100 resistor at the receiver (fpga). scki must idle in the low state in lvds i/o mode, including when transitioning cs. the data on sdo are grouped into 24- bit packets consist - ing of an 18-bit conversion result , 3 - bit analog channel id, and 3-bit softspan code, all presented msb first. as suggested in figures 20 and 21, sdo outputs these pack - ets for all analog input channels in a sequential, circular manner. for example, the first 24-bit packet output on sdo corresponds to analog input channel 0, followed by the packets for channels 1 through 7. the data output on sdo then wraps back to channel 0, and this pattern repeats indefinitely. s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 2624 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3s4 s1s2 s0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ss1ss2 ss0 d17 d16 d15 cnv (cmos) cs = pd = 0 234818 f20 don?t care t acq busy (cmos) scko (lvds) sdo (lvds) scki (lvds) sdi (lvds) don?t care sample n t cnvl t cyc recommended data transaction window sample n + 1 softspan configuration word for conversion n + 1 channel 0 24-bit packet conversion n channel 1 24-bit packet conversion n channel 7 24-bit packet conversion n conversion result channel id softspan 186185 187 188 189 190 191 192 d0 ss1ss2 ss0 d17 channel 0 24-bit packet conversion n conversion result channel id softspan t skew t cnvh t sckih t sckil t busylh t dsdoscki t hsdoscki t dsdobusyl t ssdiscki t ssdiscki t hsdiscki t hsdiscki t quiet t scki t conv c2 c1 c0 c2 c1 c0 figure 20. serial lvds i/o mode a pplica t ions i n f or m a t ion ltc 2348-18 234818f
36 for more information www.linear.com/ltc2348-18 cs (cmos) pd = 0 don?t care busy (cmos) scko (lvds) sdo (lvds) scki (lvds) sdi (lvds) don?t care don?t care don?t care 234818 f21 hi-z hi-z channel 0 packet channel 1 packet channel 2 packet channel 3 packet (partial) hi-z hi-z new softspan configuration word (overwrites internal config register) two all-zero words and one partial word (internal config register retains current value) t en t dis figure 21. internal softspan configuration register behavior. serial lvds bus response to cs serial lvds output data capture as shown in table 3, full 200ksps per channel throughput can be achieved with a 180mhz scki frequency by captur - ing eight packets (96 scki cycles total) of ddr data from sdo. the ltc2348-18 supports lvds scki frequencies up to 250mhz. programming the softspan configuration register in lvds i/o mode the internal 24-bit softspan configuration register con - trols the softspan range for all analog input channels of the ltc2348-18. the default state of this register after power-up or resetting the device is all ones , configuring each channel to convert in softspan 7, the 2.5 ? v refbuf range ( see table 1a). the state of this register may be modified by providing a new 24- bit softspan configuration word on sdi during the data transaction window shown in figure 20. new softspan configuration words are only accepted within this recommended data transaction win - dow, but softspan changes take effect immediately with no additional analog input settling time required before starting the next conversion. setting a channels softspan code to ss [2:0] = 000 immediately disables the channel, resulting in a corresponding reduction in t conv on the next conversion. similarly, enabling a previously disabled chan - nel requires no additional analog input settling time before starting the next conversion. the mapping between the serial softspan configuration word, the internal softspan configuration register, and each channel s 3-bit softspan code is illustrated in figure 19. if fewer than 24 scki edges (rising plus falling) are provided during a data transaction window, the partial word received on sdi will be ignored and the softspan configuration register will not be updated. if exactly 24 scki edges are provided, the softspan configuration register will be updated to match the received softspan configuration word, s[23:0]. the one exception to this behavior occurs when s[23:0] is all zeros. in this case, the softspan configuration register will not be updated, allowing applications to retain the current softspan con - figuration state by idling sdi low. if more than 24 scki ed ges are provided during a data transaction window , each complete 24- bit word received on sdi will be interpreted as a new softspan configuration word and applied to the softspan configuration register as described above. any partial words are ignored. typically, applications will update the softspan configura - tion register in the manner shown in figures 20 and 21. after the opening of a new data transaction window at the falling edge of busy , the user supplies a 24-bit ddr softspan configuration word on sdi during the first 12 scki cycles. this new word overwrites the internal con - figuration register contents following the 12 th scki falling edge. the user then holds sdi low for the remainder of the data transaction window causing the register to retain its contents regardless of the number of additional scki cycles applied. softspan settings may be retained across multiple conversions by holding sdi low for the entire data transaction window, regardless of the number of scki cycles applied. a pplica t ions i n f or m a t ion ltc 2348-18 234818f
37 for more information www.linear.com/ltc2348-18 to obtain the best performance from the ltc2348-18, a four-layer printed circuit board (pcb) is recommended. layout for the pcb should ensure the digital and analog signal lines are separated as much as possible. in particu - lar, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc . also minimize the length of the refbuf to gnd (pin 20) bypass capacitor return loop, and avoid routing cnv near signals which could potentially disturb its rising edge. recommended layout the following is an example of a recommended pcb layout. a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc2094a, the evaluation kit for the ltc2348-18. b oar d l ayou t figure 22. partial top silkscreen figure 24. partial layer 2, ground plane figure 23. partial layer 1, top layer figure 25. partial layer 3, power plane ltc 2348-18 234818f
38 for more information www.linear.com/ltc2348-18 b oar d l ayou t figure 26. partial layer 4, bottom layer figure 27. partial bottom silkscreen ltc 2348-18 234818f
39 for more information www.linear.com/ltc2348-18 b oar d s che m a t ic ltc 2348-18 234818f
40 for more information www.linear.com/ltc2348-18 b oar d s che m a t ic ltc 2348-18 234818f
41 for more information www.linear.com/ltc2348-18 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. lx48 lqfp 0113 rev a 0 ? 7 11 ? 13 0.45 ? 0.75 1.00 ref 11 ? 13 9.00 bsc a a 7.00 bsc 1 2 7.00 bsc 9.00 bsc 48 1.60 max 1.35 ? 1.45 0.05 ? 0.15 0.09 ? 0.20 0.50 bsc 0.17 ? 0.27 gauge plane 0.25 note: 1. package dimensions conform to jedec #ms-026 package outline 2. dimensions are in millimeters 3. dimensions of package do not include mold flash. mold flash shall not exceed 0.25mm on any side, if present 4. pin-1 indentifier is a molded indentation, 0.50mm diameter 5. drawing is not to scale see note: 4 c0.30 ? 0.50 r0.08 ? 0.20 7.15 ? 7.25 5.50 ref 1 2 5.50 ref 7.15 ? 7.25 48 package outline recommended solder pad layout apply solder mask to areas that are not soldered section a ? a 0.50 bsc 0.20 ? 0.30 1.30 min lx package 48-lead plastic lqfp (7mm 7mm) (reference ltc dwg # 05-08-1760 rev a) e3 ltcxxxx lx-es q_ _ _ _ _ _ xxyy tray pin 1 bevel package in tray loading orientation component pin ?a1? ltc 2348-18 234818f
42 for more information www.linear.com/ltc2348-18 ? linear technology corporation 2015 lt 0515 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2348-18 r ela t e d p ar t s typical a pplica t ion part number description comments adcs ltc2378-20/ltc2377-20/ ltc2376-20 20-bit, 1msps/500ksps/250ksps, 0.5ppm inl serial, low power adc 2.5 v supply, 5v fully differential input, 104db snr, msop-16 and 4mm 3mm dfn-16 packages ltc2338-18 /ltc2337-18/ ltc2336-18 18-bit, 1msps/500ksps/250ksps, serial, low power adc 5 v supply, 10.24v fully differential input, 100db snr, msop-16 package ltc2328-18 /ltc2327-18/ ltc2326-18 18-bit, 1msps/500ksps/250ksps, serial, low power adc 5 v supply, 10.24v pseudo-differential input, 95db snr, msop-16 package ltc2373-18 /ltc2372-18 18-bit, 1msps/500ksps, 8-channel, serial adc 5v supply, 8 channel multiplexed, configurable input range, 100db snr, dgc, 5mm 5mm qfn-32 package ltc2379-18/ltc2378-18/ ltc2377-18/ltc2376-18 18-bit,1.6msps/1msps/500ksps/250ksps, serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc, pin compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380-16/ltc2378-16/ ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps, serial, low power adc 2.5v supply, differential input, 96.2db snr, 5v input range, dgc, pin compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2389-18/ltc2389-16 18-bit/16-bit, 2.5msps, parallel/serial adc 5v supply, pin-configurable input range, 99.8db/96db snr, parallel or serial i/o 7mm 7mm lqfp-48 and qfn-48 packages ltc1859 /ltc1858/ ltc1857 16-/14-/12-bit, 8-channel, 100ksps, serial adc 10v, softspantm, single-ended or differential inputs, single 5v supply, ssop-28 package ltc1609 16-bit, 200ksps serial adc 10v, configurable unipolar/bipolar input, single 5v supply, ssop-28 and so-20 packages ltc1606/ltc1605 16-bit, 250ksps/100ksps, parallel adc 10v input, 5v supply, 75mw/55mw, ssop-28 and so-28 packages dacs ltc2756/ltc2757 18-bit, serial/parallel i out softspan dac 1lsb inl/dnl, software-selectable ranges, ssop-28/7mm 7mm lqfp-48 package ltc 2641 16-bit/14-bit/12-bit single serial v out dac 1lsb inl/dnl, msop-8 package, 0v to 5v output ltc2668 16-channel 16-/12-bit 10 v v out softspan dacs 4lsb inl, precision reference 10ppm/ c max, 6mm 6mm qfn-40 package references ltc6655 precision low drift low noise buffered reference 5v /2.5v /2.048v /1.25v , 2ppm/c , 0.25ppm peak- to- peak noise, msop-8 package ltc6652 precision low drift low noise buffered reference 5v /2.5v /2.048v /1.25v , 5ppm/c , 2.1ppm peak- to- peak noise, msop-8 package amplifiers lt1468/lt1469 single/ dual 90mhz, 22v /s , 16-bit accurate op amp low input offset: 75v/125v lt1354/lt1355/lt1356 single/ dual/ quad 1 ma, 12mhz, 400v / s op amp good dc precision, stable with all capacitive loads ?5v ?5v 31v 31v ltc2348-18 234818 f07a only channel 0 shown for clarity 24v 0v arbitrary + ? + ? 0.1f 0.1f 0.1f 47f in0 + in0 ? ? lt1124 ? lt1124 v cc refin refbuf v ee lowpass filters bw ~ 500khz 6.6nf 6.6nf 49.9 49.9 549 18pf 18pf in + in ? 2.49k 2.49k common mode input range differential mode input range: 500mv digitize differential signals over a wide common mode range ltc 2348-18 234818f

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